Design and Non-linear Modelling of CMOS Multipliers for Analog VLSI Implementation of Neural Algorithms

The analog VLSI implementation looks an attractive way for implementing Artiicial Neural Networks; in fact, it gives small area, low power consumption and compact design of neural computational primitive circuits. On the other hand, major drawbacks result to be the low computational accuracy and the non-linear behaviour of analog circuits. In this paper, we present the design and the detailed behavioural models of CMOS multipliers for the analog VLSI implementation of neural algorithms. The circuits implement the feed-forward operations of the Multi Layer Perceptron architecture and of the Back Propagation (on-chip learning) algorithm; they operate in the subthreshold regime to obtain a low power consumption and high dynamic range of weights. The circuit behavioural models take into account: i) non-linearity eeects; ii) environmental eeects (variations of temperature and of signal reference voltage). The models that we present in this paper, are used in the behavioural validation of the proposed architecture.